1. Technical Field
The present invention relates to a method for forming a stacking structure, and more particularly, to a method for forming a stacking structure having a rutile phase titanium oxide by forming a praseodymium oxide interface layer prior to the titanium oxide crystal growth.
2. Background
The performance of complementary metal-oxide-semiconductor (CMOS) devices has continued to improve over four decades in accordance with the prediction of Moore's Law of scaling. As the number of devices on an integrated circuit has increased exponentially, the minimum feature size in a transistor has decreased exponentially each year. Dynamic random access memory (DRAM) is another common device which constitutes memory cells, each having a capacitor that hold a charge indicative of a data value in the memory cell. One of the common features of the two devices mentioned above is a generic metal-insulator-metal (MIM) structure. Keeping pace with the rapid reduction of the size of devices, the thickness of the insulator layer, typically silicon dioxide, has decreased to under 2 nm. At this level of thickness, a substantial leakage current occurs due to direct tunneling of the electrons through the insulator layer. A solution in this field is to find an alternative material which can provide a greater thickness to prevent the tunneling form happening and at the same time, possessing a higher relative permittivity, or dielectric constant, to maintain a required capacitance. The relation of the capacitance to the thickness and dielectric constant can be described in the following equation:C=∈0∈rA/t, where C is capacitance, ∈0 is vacuum permittivity, ∈r is relative permittivity or dielectric constant, A is the area of the metal-insulator interface, and t is the thickness of the insulator. In light of the equation, maintaining ∈r and t at a predetermined ratio is necessary to discover an effective production method of a high dielectric constant material with a sufficient thickness. In other words, a material with inherently low leakage current and a dielectric constant high enough to maintain a consistent ratio of (∈r/t) turns out to be an ideal target in solving this aspect of the microelectronic scaling problem.
Node dielectrics for beyond 3×nm DRAM require a dielectric constant over 70, which makes titanium dioxide (TiO2) an ideal candidate for this purpose. TiO2 occurs in nature as three well-known phases—rutile, anatase, and brooktie, wherein the rutile phase TiO2 is reported to have a dielectric constant of between 90 and 170, depending on formation conditions. However, current industrial production methods use atomic layer deposition (ALD) to produce TiO2, while ALD TiO2 inherently forms anatase phase, which is a low dielectric constant alternative, unless formation is performed using a template substrate, doping, high temperature ALD, or post deposition annealing at temperatures greater than 600 degrees Celsius.
The method of using template substrate to form rutile phase TiO2 suffers from several drawbacks, for example, in FIG. 1, an ALD process using TiCl4 as Ti precursor and H2O as an oxidant over a template substrate requires a thickness of at least 10 nm for the rutile phase TiO2 to be visible in a grazing angle X-ray diffraction. In addition to the large minimum thickness, a high processing temperature, as shown in FIG. 2, is required during production. FIG. 2 is a grazing angle X-ray diffraction showing different TiO2 layers with various thicknesses and processing temperatures. It can be seen that production conditions of 70 angstrom and 450 degrees Celsius create a prominent rutile phase TiO2 peak of around 27.5 two theta. A high processing temperature causes the rutile phase to form with a rough morphology, creating an inferior structure in terms of material density with increased leakage current. In addition, an ALD process using TiCl4 as Ti precursor and O3 as an oxidant over a template substrate not only delivers a low deposition rate but also incurs a risk of oxidizing or etching the under layer. For example, ruthenium contamination occurs in rutile phase TiO2 due to the existence of an underlying ruthenium/ruthenium oxide layer.
Other methods like doping and post deposition annealing also create disadvantages in terms of microelectronic processing. For instance, doping silicon or zirconium during the ALD formation of TiO2 is hard to control, and suffers from low throughput and high cost, while additional thermal treatment to the CMOS device can add mechanical stress to the entire underlying structure.
There is a need by the industry for a new formation method other than a template substrate, doping, or excessive annealing process that allows a thin rutile phase TiO2 with high quality crystallinity to be formed. In response to such need, the present disclosure seeks to demonstrate a special structure for rutile phase TiO2 formation.